Conventionally, depletion type MOS transistors have been used to form reference voltage circuits with high output voltage accuracy. The depletion type MOS transistor is a device that is formed by implanting impurity ions into an enhancement type MOS transistor so that current can flow even when a gate-source voltage is zero. A masked ROM is a device that is formed by changing part of MOS transistors arranged in the form of a matrix into resistance. Conventionally, in a power management-associated apparatus, such as a portable equipment, a digital circuit having a masked ROM and a reference voltage generating circuit supplying power to the digital circuit are installed in different IC chips.
In such a power management-associated apparatus, such as a portable equipment, however, it is desirable to provide such a digital circuit comprised of a depletion type MOS transistor in a single IC chip. It is also desirable to minimize the steps of manufacturing the depletion type MOS transistor to reduce number of parts and cost, while simplifying the manufacturing process.
Accordingly, there is a need for a semiconductor integrated circuit device that integrates the depletion MIS transistor, the transistor forming a masked ROM, and a submicron CMOS on a single semiconductor substrate, while minimizing the steps of manufacturing the same. The present invention addresses this need.
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit device that is equipped with a depletion type MIS transistor and a transistor forming a masked ROM. Further a submicron CMOS can be integrated with these transistors in a single or common semiconductor substrate.
One aspect of the present invention is a semiconductor integrated circuit device. This device can include a semiconductor substrate having a principal side, a well region of at least a first-conductivity type, a first transistor of MIS depletion type, and a second transistor forming part of a masked ROM.
The first transistor can have a first source region and a first drain region of a second-conductivity-type formed in the well region. A first channel region can be interposed between the first source and drain regions and a gate insulating film can be formed over the first channel region, and a first gate electrode can be formed on the first channel region over the gate insulating film. The first channel region has an impurity concentration that permits current to flow when a gate-source voltage is zero.
The second transistor can have a second channel region having the same impurity concentration as the first channel region formed in the well region. A second source region and a drain region of a second-conductivity-type respectively can be formed at both sides of the second channel region, and a second gate electrode can be formed on the second channel region over the gate insulating film.
The semiconductor integrated circuit device can further include a first LDD region of a second-conductivity-type having a lower impurity concentration than the first source region or the first drain region, formed between the first channel region and the first source region and between the first channel and the first drain region. It can further include a second LDD region of a second-conductivity-type having a lower impurity concentration than the second source region or the second drain region, formed between the second channel region and the second source region and between the second channel and the second drain region.
The semiconductor integrated circuit device can further include a punch-through stopper region of a first-conductivity-type formed between the first source region and the first drain region and between the second source region and the second drain region.
The semiconductor integrated circuit device can further include an enhancement type NMOS transistor and an enhancement type PMOS transistor. The NMOS transistor can be formed over the well region, which has a P type well region formed over the principal side of the semiconductor substrate, and can include a third source region of an N type and a third drain region an N type formed in the P type well region, and a third channel region interposed between the third source and drain regions, a third LDD region of an N type having a lower impurity concentration than the third source region or the third drain region formed between the third channel region and the third source region and between the third channel region and the third drain region, a third gate electrode formed on the third channel region over the gate insulating film, and a P type punch-through stopper region formed between the third source region and the third drain region.
The PMOS transistor can be formed over the well region, which has an N type well region is formed at the principal side of the semiconductor substrate, and can include a fourth source region of a P type and a fourth drain region of a P type formed in the N type well region, a fourth channel region interposed between the fourth source and drain regions, and a fourth LDD region of a P type having a lower impurity concentration than the fourth source region or the fourth drain region formed between the fourth channel region and the fourth source region and between the fourth channel region and the fourth drain region, a fourth gate electrode formed on the fourth channel region over the gate insulating film, and an N type punch-through stopper region formed between the fourth source region and the fourth drain region.
The semiconductor integrated circuit device can further include a first-conductivity-type punch-through stopper region provided between the first source region and the first drain region. The first conductivity-type punch-through stopper region also can be provided between the second source region and the second drain region.
Another aspect of the present invention is a method of manufacturing a semiconductor integrated circuit device. The method can comprise the steps of: forming the first transistor of a MIS depletion type and the second transistor forming part of a masked ROM on a single semiconductor substrate by: forming a well region of a first-conductivity-type in a first region where the first transistor is to be formed and a second region where the second transistor is to be formed, selectively oxidizing the regions where the first and second transistors are to be formed, implanting impurity ions of a first-conductivity-type in the regions where the first and second transistors are to be formed, implanting impurity ions of a second-conductivity-type in the regions where the first and second transistors are to be formed to permit current to flow when a gate-source voltage of the first transistor is zero, and forming the gate insulating film, gate electrode, and source and drain regions of a second-conductivity-type in each of the first and second transistors.